1. Field of the Invention
The present invention relates to an analog-to-digital converter (A/D converter) for converting an analog signal to a digital signal, and particularly to a circuit configuration of an interpolation circuit which is one of its component circuits.
2. Description of the Background Art
The role of interpolation circuits in A/D converters will now be described. The A/D converters include the folding interpolation architecture A/D converter shown in FIG. 15.
As shown in FIG. 15, a reference voltage group 111 includes N (.gtoreq.2) reference voltages Vref.sub.1, to Vref.sub.N, in which the reference voltages Vref.sub.1 to Vref.sub.N are outputted to the folding circuit 72 in the block B1 and J (&lt;N) of the reference voltages Vref.sub.1 to Vref.sub.N are outputted to the comparator group 84 as reference voltages Vrr.sub.1 to Vrr.sub.j for the block B2. FIG. 16 shows an A/D converter having a resolution of six bits, which is constructed on the basis of the configuration shown in FIG. 15.
In this architecture, A/D conversion is performed separately in the two circuit blocks B1 and B2. The circuit block B2 is used to achieve rough A/D conversion to determine higher-order bits in the digital code and the circuit block B1 is used to achieve detailed A/D conversion to determine lower-order bits in the digital code. The higher-order bits and lower-order bits can be combined in many combinations in that architecture, according to which the numbers of comparators, J and M, in the circuit blocks B2 and B1 vary as shown in Table 1. The circuit shown in FIG. 16 corresponds to the configuration in which J=3, M=16, and N=20 in Table 1.
TABLE 1 ##STR1##
FIG. 17 is a circuit diagram showing an example of the internal configuration of the interpolation circuit 73. The number of reference voltages, N, supplied to the folding circuit 72 changes as shown in Table 1 depending on the configuration of the interpolation circuit 73. The interpolation circuit of FIG. 17 corresponds to the fourfold interpolation in Table 1, which generates output signals V.sub.i0, V.sub.i1, V.sub.i2, V.sub.i3 (i=1, 2, 3 . . . ) from ends of the four resistors R30 provided in series between the applied input voltage V.sub.i and the input voltage V.sub.(i+1) (i=1, 2, 3 . . . ). That is to say, the interpolation circuit 73 has the fourfold interpolation function.
Next, operation of the above-described A/D converter will be described mainly about the example of structure shown in FIG. 16.
The comparators CMP.sub.i (i=1, 2, 3) in the block B2 compare an analog input voltage Vin and the respective reference voltages Vrr.sub.i (i=1, 2, 3) in magnitude, and they output "H" when the analog input signal Vin is larger than the reference voltage Vvv.sub.i, and "L" when the analog input signal Vin is smaller than the reference voltage Vrr.sub.i.
The preencoder 85 pre-encodes the outputs (comparison results) of the comparator group 84 to generate encoder control signals SP.sub.j (j=1, 2, 3, 4).
The encoder 86 determines the higher-order 2-bit digital codes D5 and D4 in accordance with the encoder control signals SP. Table 2 below shows the comparator outputs from the comparator group 84, the preencoder outputs from the preencoder 85, and the encoder outputs from the encoder 86, for various magnitude relations among the analog input signal Vin and the reference voltages Vrr.sub.1 to Vrr.sub.3.
TABLE 2 encoder Input voltage comparator outputs preencoder outputs outputs conditions CMP.sub.3 CMP.sub.2 CMP.sub.1 SP.sub.4 SP.sub.3 SP.sub.2 SP.sub.1 D5 D4 Vin &lt; Vrr.sub.1 L L L L L L H L L Vrr.sub.1 .ltoreq. Vin &lt; Vrr.sub.2 L L H L L H L L H Vrr.sub.2 .ltoreq. Vin &lt; Vrr.sub.3 L H H L H L L H L Vrr.sub.3 .ltoreq. Vin H H H H L L L H H
The folding circuit 72 in the block B1 performs analog computation on the basis of the analog input signal Vin and the reference voltages Vref.sub.k (k=1, 2 . . . 20) and transmits four sets of output signal pairs VF.sub.m and VFB.sub.m (m=1, 2, 3, 4) (not shown in FIG. 16) to the interpolation circuit 73 in the next stage. The output signal VFB.sub.m is a complementary signal of VF.sub.m.
The above-stated analog computation performed by the folding circuit 72 has the output characteristics as shown in FIG. 18, which generates the output signal pairs VF.sub.n and VFB.sub.n (n=1, 2, 3, 4) from the analog input signal Vin and the reference voltages Vref.sub.n, Vref.sub.n+3, Vref.sub.n+6, Vref.sub.n+9, Vref.sub.n+12 (n=1, 2, 3, 4). The output signal pair VF.sub.n and VFB.sub.n are complementary signals as a pair of differential signals.
The interpolation circuit 73 voltage-divides the output signals on the basis of the four signal pairs of the output signals VF.sub.n and VFB.sub.n (n=1, 2, 3, 4) from the folding circuit 72 to generate and transfer 16 signal pairs VI.sub.y and VIB.sub.y (y=1, 2 . . . 16) (not shown in FIG. 16) to the comparator group 74 in the next stage. Table 3 shows the relation between the signal pairs VF.sub.n and VFB.sub.n and VI.sub.y and VIB.sub.y.
TABLE 3 k VI.sub.k VIB.sub.k 1 VF.sub.1 VFB.sub.1 2 VF.sub.1 .times. 3/4 + VF.sub.2 .times. 1/4 VFB.sub.1 .times. 3/4 + VFB.sub.2 .times. 1/4 3 VF.sub.1 .times. 1/2 + VF.sub.2 .times. 1/2 VFB.sub.1 .times. 1/2 + VFB.sub.2 .times. 1/2 4 VF.sub.1 .times. 1/4 + VF.sub.2 .times. 3/4 VFB.sub.1 .times. 1/4 + VFB.sub.2 .times. 3/4 5 VF.sub.2 VFB.sub.2 6 VF.sub.2 .times. 3/4 + VF.sub.3 .times. 1/4 VFB.sub.2 .times. 3/4 + VFB.sub.3 .times. 1/4 7 VF.sub.2 .times. 1/2 + VF.sub.3 .times. 1/2 VFB.sub.2 .times. 1/2 + VFB.sub.3 .times. 1/2 8 VF.sub.2 .times. 1/4 + VF.sub.3 .times. 3/4 VFB.sub.2 .times. 1/4 + VFB.sub.3 .times. 3/4 9 VF.sub.3 VFB.sub.3 10 VF.sub.3 .times. 3/4 + VF.sub.4 .times. 1/4 VFB.sub.3 .times. 3/4 + VFB.sub.4 .times. 1/4 11 VF.sub.3 .times. 1/2 + VF.sub.4 .times. 1/2 VFB.sub.3 .times. 1/2 + VFB.sub.4 .times. 1/2 12 VF.sub.3 .times. 1/4 + VF.sub.4 .times. 3/4 VFB.sub.3 .times. 1/4 + VFB.sub.4 .times. 3/4 13 VF.sub.4 VFB.sub.4 14 VF.sub.4 .times. 3/4 + VFB.sub.1 .times. 1/4 VFB.sub.4 .times. 3/4 + VF.sub.1 .times. 1/4 15 VF.sub.4 .times. 1/2 + VFB.sub.1 .times. 1/2 VFB.sub.4 .times. 1/2 + VF.sub.1 .times. 1/2 16 VF.sub.4 .times. 1/4 + VFB.sub.1 .times. 3/4 VFB.sub.4 .times. 1/4 + VF.sub.1 .times. 3/4
As shown in Table 3, for example, while VI.sub.1 is equal to VF.sub.1, VI.sub.2 is the voltage which is most close to VF.sub.1 among the four fractions of the voltage range of VF.sub.1 and VF.sub.2 (VI.sub.2 =VF.sub.1.times.3/4+VF.sub.2.times.1/4), and VI.sub.3 is the middle voltage among the four fractions of the voltage range of VF.sub.1 and VF.sub.2 (VI.sub.3 =VF.sub.1.times.1/2+VF.sub.2.times.1/2).
The comparators CMPD.sub.y (y=1, 2 . . . 16) in the comparator group 74 compare the signal pairs VI.sub.y and VIB.sub.y in magnitude. They output "H" when the signal VI.sub.y is larger than the signal VIB.sub.y and "L" in the opposite case.
The preencoder 75 generates encoder control signals SPD.sub.y (y=1, 2 . . . 16) on the basis of the outputs of the comparator group 74 (not shown in FIG. 16).
The encoder 76 determines and outputs the lower-order four-bit digital codes D3, D2, D1, D0 according to the encoder control signals SPD.
Tables 4 to 6 show the comparator outputs from the comparator group 74 the preencoder outputs from the preencoder 75, and the encoder outputs from the encoder 76, for part of the conditions of the magnitude relation among the analog input signal Vin and the reference voltages Vref.sub.k.
TABLE 4 C1 = Vref.sub.2 .ltoreq. Vin &lt; Vref.sub.2 .times. 3/4 + Vref.sub.3 .times. 1/4 C2 = Vref.sub.2 .times. 3/4 + Vref.sub.3 .times. 1/4 .ltoreq. Vin &lt; Vref.sub.2 .times. 1/2 + Vref.sub.3 .times. 1/2 C3 = Vref.sub.2 .times. 1/2 + Vref.sub.3 .times. 1/2 .ltoreq. Vin &lt; Vref.sub.2 .times. 1/4 + Vref.sub.3 .times. 3/4 C4 = Vref.sub.2 .times. 1/4 + Vref.sub.3 .times. 3/4 .ltoreq. Vin &lt; Vref.sub.3 C5 = Vref.sub.3 .ltoreq. Vin &lt; Vref.sub.3 .times. 3/4 + Vref.sub.4 .times. 1/4 C6 = Vref.sub.3 .times. 3/4 + Vref.sub.4 .times. 1/4 .ltoreq. Vin &lt; Vref.sub.3 .times. 1/2 + Vref.sub.4 .times. 1/2 C7 = Vref.sub.3 .times. 1/2 + Vref.sub.4 .times. 1/2 .ltoreq. Vin &lt; Vref.sub.3 .times. 1/4 + Vref.sub.4 .times. 3/4 C8 = Vref.sub.3 .times. 1/4 + Vref.sub.4 .times. 3/4 .ltoreq. Vin &lt; Vref.sub.4 C9 = Vref.sub.4 .ltoreq. Vin &lt; Vref.sub.4 .times. 3/4 + Vref.sub.5 .times. 1/4 C10 = Vref.sub.4 .times. 3/4 + Vref.sub.5 .times. 1/4 .ltoreq. Vin &lt; Vref.sub.4 .times. 1/2 + Vref.sub.5 .times. 1/2 C11 = Vref.sub.4 .times. 1/2 + Vref.sub.5 .times. 1/2 .ltoreq. Vin &lt; Vref.sub.4 .times. 1/4 + Vref.sub.5 .times. 3/4 C12 = Vref.sub.4 .times. 1/4 + Vref.sub.5 .times. 3/4 .ltoreq. Vin &lt; Vref.sub.5 C13 = Vref.sub.5 .ltoreq. Vin &lt; Vref.sub.5 .times. 3/4 + Vref.sub.6 .times. 1/4 C14 = Vref.sub.5 .times. 3/4 + Vref.sub.6 .times. 1/4 .ltoreq. Vin &lt; Vref.sub.5 .times. 1/2 + Vref.sub.6 .times. 1/2 C15 = Vref.sub.5 .times. 1/2 + Vref.sub.6 .times. 1/2 .ltoreq. Vin &lt; Vref.sub.5 .times. 1/4 + Vref.sub.6 .times. 3/4 C16 = Vref.sub.5 .times. 1/4 + Vref.sub.6 .times. 3/4 .ltoreq. Vin &lt; Vref.sub.6
TABLE 5 comparator CMPD.sub.i outputs Input i = i = i = i = i = i = i = condition 16 15 14 13 12 11 10 i = 9 i = 8 i = 7 i = 6 i = 5 i = 4 i = 3 i = 2 i = 1 . . . . . . C1 L L L L L L L L L L L L L L L H C2 L L L L L L L L L L L L L L H H C3 L L L L L L L L L L L L L H H H C4 L L L L L L L L L L L L H H H H C5 L L L L L L L L L L L H H H H H C6 L L L L L L L L L L H H H H H H C7 L L L L L L L L L H H H H H H H C8 L L L L L L L L H H H H H H H H C9 L L L L L L L H H H H H H H H H C10 L L L L L L H H H H H H H H H H C11 L L L L L H H H H H H H H H H H C12 L L L L H H H H H H H H H H H H C13 L L L H H H H H H H H H H H H H C14 L L H H H H H H H H H H H H H H C15 L H H H H H H H H H H H H H H H C16 H H H H H H H H H H H H H H H H . . . . . .
TABLE 6 INPUT PREENCODER OUTPUT SPi ENCODER CONDI- i = i = i = OUTPUT TION 16 15 14 i = 13 i = 12 i = 11 i = 10 i = 9 i = 8 i = 7 i = 6 i = 5 i = 4 i = 3 i = 2 i = 1 D3 D2 D1 D0 .iota. .iota. .iota. C1 L L L L L L L L L L L L L L L H L L L L C2 L L L L L L L L L L L L L L H L L L L H C3 L L L L L L L L L L L L L H L L L L H L C4 L L L L L L L L L L L L H L L L H L H H C5 L L L L L L L L L L L H L L L L L H L L C6 L L L L L L L L L L H L L L L L L H L H C7 L L L L L L L L L H L L L L L L L H H L C8 L L L L L L L L H L L L L L L L L H H H C9 L L L L L L L H L L L L L L L L H L L L C10 L L L L L L H L L L L L L L L L H L L H C11 L L L L L H L L L L L L L L L L H L H L C12 L L L L H L L L L L L L L L L L H L H H C13 L L L H L L L L L L L L L L L L H H L L C14 L L H L L L L L L L L L L L L L H H L H C15 L H L L L L L L L L L L L L L L H H H L C16 H L L L L L L L L L L L L L L L H H H H .iota. .iota. .iota.
Next, the circuit configuration of the interpolation circuit 73, particularly its layout, will be described. FIG. 19 is an explanation diagram showing the layout of the interpolation circuit 73. In FIG. 19, the circuit blocks C.sub.n (n=1, 2, 3, 4) are sub-circuits in the folding circuit 72, each outputting a signal pair VF.sub.n and VFB.sub.n. The 32 resistor elements RR1 to RR32 are resistor elements for interpolation, and L50 and L51 are wiring for connecting the adjacent resistor elements RRi and RR(i+1) (i=1 to 15), and RR32 and RR1.
Now problems of the conventional layout of the interpolation circuit 73 shown in FIG. 19 will be described. For convenience, one of the resistor elements RR1 to RR32 is referred to as a resistor element RR.
The output voltages VI.sub.x and VIB.sub.x (x=1, 5, 9, 13) of the interpolation circuit 73 correspond to VF.sub.([x/4]+1) ([x/4] is the quotient of x divided by 4) and VFB.sub.([/4])+1).
The output voltages VI.sub.y and VIB.sub.y (y=2, 3, 4, 6, 7, 8, 10, 11, 12) of the interpolation circuit 73 are obtained by dividing the voltage range between VF.sub.([(x-1)/4]+1) and VF, .sub.[(x-1)/4+2], or between VFB.sub.[(x-1)/4+1] and VFB.sub.[(x-1)/4+2] by the sum of four resistor elements RR (resistance value R) and resistance components rr of four wiring L50 (resistance value r), i.e. 4.times.(R+r).
The output voltages VI.sub.z and VIB.sub.z (z=14, 15, 16) of the interpolation circuit 73 are obtained by dividing the voltage range between VF.sub.4 and VFB.sub.1 or between VFB.sub.4 and VF.sub.1 by the sum of four resistor elements RR, three wiring 50, and resistance component rr' of one wiring L51 (resistance value r'), i.e. 4R+3r+r'.
The resistance value r and the resistance value r' take different values since the wiring L50 and the wiring L51 differ in length, and therefore the division is not uniform between the output voltages VI.sub.y and VIB.sub.y (y=2, 3, 4, 6, 7, 8, 10, 11, 12) and VI.sub.z and VIB.sub.z (z=14, 15, 16) of the interpolation circuit 73, which deteriorates accuracy of the output voltages.
The time required for the outputs of the interpolation circuit 73 to vary on the basis of the output signals VF.sub.n and VFB.sub.n from the circuit blocks C.sub.n (n=1, 2, 3, 4) is proportional to the product of the resistance value and capacitance value of the resistor elements and wiring connected to the respective input terminals of the interpolation circuit 73.
For VI.sub.y and VIB.sub.y (y=2, 3, 4, 6, 7, 8, 10, 11, 12) generated on the basis of at least one of the output signals of the circuit blocks C.sub.2 and C.sub.3, it is proportional to the product of the resistance value 4.times.(R+r) and the total quantity C of the parasitic capacitance. On the other hand, for the output signals VI.sub.z and VIB.sub.z (z=14, 15, 16) of the interpolation circuit which are generated on the basis of the output signals of the circuit blocks C.sub.1 and C.sub.4, the time required for change is proportional to the product of the resistance value 4R+3r+r' and the total quantity C' of parasitic capacitance of the wiring. The resistance values r and r' take different values since the wiring L50 and L51 differ in length. Further, the total quantities of the parasitic capacitance, C and C', also take different values since the wiring L50 and L51 differing in length have different parasitic capacitance values.
Accordingly the time required for change of the first output signal group VI.sub.y and VIB.sub.y (y=2, 3, 4, 6, 7, 8, 10, 11, 12) of the interpolation circuit 73 differs from the time required for change of the second output signal group VI.sub.z and VIB.sub.z (z=14, 15, 16). The comparators CMPD.sub.k (k=1, 2 . . . 16) in the comparator group 74 following the interpolation circuit 73 all perform the magnitude comparing operation by the same timing. Therefore, when the output signals from the interpolation circuit 73 vary at different points of time, the time difference .DELTA.T causes errors in the outputs of the comparator group 74, which deteriorates the converting accuracy of the A/D converter.
The deterioration of conversion accuracy caused by the unequal timing will be described below. For example, assume that, in a certain comparison, the voltage difference between the pair of output signals VF.sub.1 and VFB.sub.1 from the circuit block C.sub.1 is originally +V.sub.1 +.DELTA.V at the last moment of the comparison period T and the voltage difference between the pair of output signals VF.sub.2 and VFB.sub.2 from the block C.sub.2 is -V.sub.1.
In this condition, when 0&lt;.DELTA.V&lt;2V.sub.1, for example, the magnitude relation of VI.sub.1 &gt;VIB.sub.1, VI.sub.2 &gt;VIB.sub.2, VI.sub.3 &gt;VIB.sub.3, VI.sub.4 &lt;VIB.sub.4, VI.sub.5 &lt;VIB.sub.5 holds in the outputs of the interpolation circuit 73. Then, in normal operation, the outputs from the comparators CMPD.sub.1 to CMPD.sub.3 are at "H" and the outputs of the CMPD.sub.4 and CMPD.sub.5 are at "L."
However, the time difference .DELTA.T exists between the times required for the output signals to change from the voltages in the previous comparison period T. Then, suppose that, at the last moment of the comparison period T, the voltage difference between the pair of output signals VF.sub.1 and VFB.sub.1 takes a value +V.sub.1 +.DELTA.V' (&gt;2V.sub.1), instead of the normal value +V.sub.1 +.DELTA.V, and the voltage difference between VF.sub.2 and VFB.sub.2 takes the value -V.sub.1.
In this case, in the outputs of the interpolation circuit 73, the magnitude relation of VI.sub.1 &gt;VIB.sub.1, VI.sub.2 &gt;VIB.sub.2, VI.sub.3 &gt;VIB.sub.3, VI.sub.4 &gt;VIB.sub.4, VI.sub.5 &lt;VIB.sub.5 holds, and then the outputs of the comparators CMPD.sub.1 to CMPD.sub.4 are at "H" and the output of the CMPD.sub.5 is at "L." Thus an error occurs with respect to the normal value. This error deteriorates the conversion accuracy of the A/D converter.
Especially, as the comparison period T for the comparators is shorter in a higher speed A/D converter, the time difference .DELTA.T in variation among the output signals of the interpolation circuit 73 occupies a larger part in the comparison period T, and the output error of the comparators becomes still larger.
As another example of the layout other than that shown in FIG. 19, the resistors RR13 to RR16 (and wiring L52 between them) between VF.sub.4 and VFB.sub.1 between the blocks C.sub.4 and C.sub.1 and the resistors RR29 to RR32 (and wiring L52 between them) between VFB.sub.4 and VF.sub.1 are arranged as shown in FIG. 20 so that the wiring L50 and L52 have reduced differences in resistance value and parasitic capacitance value. This layout is the same as that shown in FIG. 19 in other respects.
However, this layout cannot avoid the deterioration of the A/D conversion accuracy, since the lengths of the wiring L50 and the wiring L52 still differ considerably also in this case.